/*	$Id: expr.h 7 2008-07-29 02:58:11Z phrakt $	*/
/*
 * Copyright (c) 2005 Jean-Francois Brousseau <jfb@openbsd.org>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. The name of the author may not be used to endorse or promote products
 *    derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
 * THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL  DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
/*
 * Expression engine
 *
 * Packet Forge expressions are managed internally as a small set of operations
 * Each operation is encoded over 32 bits, with the following layout:
 *
 * 0          5     8
 * +----------+-----+
 * |  Opcode  | Sig |
 * +----------+-----+
 *
 * Instructions are defined by two fields: the operation code and the
 * signature, which describes the number and type of operands.
 */

#ifndef _PFORGE_EXPR_H_
#define _PFORGE_EXPR_H_

#include <sys/types.h>

#include "pkt.h"
#include "pforge.h"

#define PFEX_VM_NREG        16
#define PFEX_VM_MAXINS    1024

#define PFEX_OPMASK       0x1f
#define PFEX_SIGMASK      0xe0

/* instruction signatures (type and amount of operands) */
#define PFEX_SIG_I	0x01
#define PFEX_SIG_R	0x02
#define PFEX_SIG_II	0x03
#define PFEX_SIG_IR	0x04
#define PFEX_SIG_RI	0x05
#define PFEX_SIG_RR	0x06


/* operation codes */
#define PFEX_OP_NOOP	0x00
#define PFEX_OP_LDB	0x01	/* LoaD Byte */
#define PFEX_OP_LDW	0x02	/* LoaD Word */
#define PFEX_OP_LDD	0x03	/* LoaD Double word */
#define PFEX_OP_ADD	0x04	/* ADD */
#define PFEX_OP_SUB	0x05	/* SUBtract */
#define PFEX_OP_MUL	0x06	/* MULtiply */
#define PFEX_OP_DIV	0x07	/* DIVide */
#define PFEX_OP_AND	0x08	/* AND */
#define PFEX_OP_OR	0x09	/* OR */
#define PFEX_OP_XOR	0x0a	/* eXclusive OR */
#define PFEX_OP_SHL	0x0b	/* SHift Left */
#define PFEX_OP_SHR	0x0c	/* SHift Right */

#define PFEX_OP_JMP
#define PFEX_OP_JIZ

#define PFEX_OP_END	0x1f	/* END execution */


/* processor status bits */
#define PFEX_PS_ZRFL	0x01
#define PFEX_PS_HALT	0x02


#define PFEX_OP_SIG(op)       (((op) >> 24) & PFEX_SIGMASK)
#define PFEX_OP_CODE(op)      (((op) >> 24) & PFEX_OPMASK)

#define PFEX_VM_HALTED(vm)    ((vm)->ev_ps & PFEX_PS_HALT)


struct pf_expr_op {
	uint32_t   opc:  5;
};

struct pf_expr {
	uint16_t    ex_len;
	uint32_t   *ex_ops;
};


struct pf_expr_vm {
	uint32_t   ev_acc;			/* accumulator */
	uint32_t   ev_ind;
	uint16_t   ev_pc;			/* program counter */
	uint16_t   ev_ps;			/* processor status */
	uint32_t   ev_gr[PFEX_VM_NREG];	/* general registers */
};

#endif	/* _PFORGE_EXPR_H_ */
